All the students have to compulsory fill this form before 14/10/2017.
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Saturday, 7 October 2017
Wednesday, 20 September 2017
Tuesday, 19 September 2017
MPI Assignment for Vth sem Student 2017
GOVERNMENT ENGINEERING COLLEGE, PATAN
B.E. SEMESTER IV (CE)
MICROPROCESSOR AND INTERFACING
ASSIGNMENT
1. Draw and Explain
architecture of 8085 microprocessor in detail.
2. Explain 8085 bus
organization in detail.
3. Explain Flag
Register of 8085.
4. Give the use of following
pins .
5. a. ALE b. HOLD c.
HLDA d. READY e. TRAP f. SID
6.
Explain the following instructions of 8085. Also mention
about the addressing mode and flags the instruction affects.
a.
LHLD 1000H (2) RAL (3) DAD D (4) PUSH PSW (5)PCHL
7. What is meant by Bus?
Why is the address bus unidirectional and the data bus bidirectional ?
8.
What do you understand by the term Addressing mode? Explain
the Addressing modes supported by 8085 by giving suitable examples.
9. Explain Memory Mapped
I/O and Peripheral I/O and make the comparison between them.
10. Explain the function
of RIM and SIM instructions.
11. Write a detailed
note on Memory Classification.
12. List the four
categories of 8085 instructions that manipulate the data.
13. Explain
microprocessor operation?
14.
Explain Memory Mapped I/O and
Peripheral I/O and make the comparison between them.
15.
Draw the timing diagram of following instructions of an 8085
microprocessor. a. MVI A, 32H b.IN 00h c. STA
2050H d. DAD
16.
Define the concept of subroutine. Explain the CALL and RET
instructions of the 8085 microprocessor with example.
17.
What is stack and stack pointer?
Explain working of PUSH and POP instruction with suitable example.
18.
How many address lines are
necessary on the chip of 2K byte memory?
19. If the memory chip size is 1024 X 4 bits, how many chips are
required to make up 2K bytes of memory?
20. The memory map of a 4K byte memory chip begins at the location
2000 H. Specify the address of the last location on the chip and the number of
pages on the chip.
21. The memory address of the last location of an 8K byte memory
chip is FFFF H. Find the starting address.
22.
What
is instruction cycle? Explain using waveforms the fetch & execute cycle
with reference of clock .
23.
Explain with a sketch how demultiplexing of AD bus takes place
24.
What is conditional &unconditional branching ? Illustrate the
answer with an example.
25.
Using diagram illustrate logic pin
out of the 8085 Microprocessor
26.
What are interrupts? List and explain the interrupt available in
microprocessor 8085?
27.
Explain how address/data lines AD0-AD7 are de-multiplexed. Draw logic diagram
to generate control signals MEMW, MEMR, IOW and IOR from IO/M,WR and RD.
28.
What is direct memory access? Explain interfacing of 8237 DMA
controller with 8085 microprocessor. What is importance of DMA?
Note:Student who get 12 or less than 12 marks in mid sem exam then submit assignment on or before 28/09/2017.
Saturday, 19 August 2017
Mid-sem Exam of Semester 5th and 7th
GOVERNMENT ENGINEERING COLLEGE, PATAN
COMPUTER SCIENCE AND ENGINEERING
DEPARTMENT
MID SEMESTER EXAMINATION TIMETABLE SEPTEMBER
-2017
SEMESTER: 5th
|
DATE
|
SUBJECT
|
Time
|
|
04/09/2017
|
2150704
: Object Oriented Programming using JAVA
|
11:30 A.M .
To
12:30 P.M.
|
|
05/09/2017
|
2150707
: Microprocessor and Interfacing
|
|
|
06/09/2017
|
2150708
: System Programming
|
|
|
|
|
SEMESTER: 7th
|
DATE
|
SUBJECT
|
Time
|
|
04/09/2017
|
2170701
: Complier Design
|
02:00 P.M.
To
03:00 P.M.
|
|
05/09/2017
|
2170709
: Information and Network Security
|
|
|
06/09/2017
|
2170710
: Mobile Computing and Wireless Communication
|
|
|
07/09/2017
|
2170712
: Image Processing
2170714
: Distributed DBMS
2170715
: Data Mining and Business Intelligence
|
EXAM CO-ORDINATOR H.O.D
GOVERNMENT ENGINEERING COLLEGE, PATAN
COMPUTER SCIENCE AND ENGINEERING
DEPARTMENT
MID SEMESTER EXAMINATION SEATING
ARRANGEMENT
SEPTEMBER -2017
SEMESTER: 5TH
|
SR.NO
|
ENROLLMENT NO.
|
Total
|
Classroom
|
|
1
|
140220107025 to 150220107038
|
35
|
306
|
|
2
|
150220107040 to 150220107085
|
35
|
307
|
|
3
|
150220107085 to 160223107003
|
35
|
314
|
|
4
|
160223107005 to 130220131089
|
32
|
316
|
SEMESTER: 7TH
|
SR.NO
|
ENROLLMENT NO.
|
Total
|
Classroom
|
|
1
|
110220131109 to 140220107044
|
31
|
306
|
|
2
|
140220107045 to 140220107082
|
31
|
307
|
|
3
|
140220107083 to 150223131003
|
28
|
314
|
|
4
|
150223131004 to 150223131042
|
28
|
316
|
SEMESTER: 7TH [Elective Subject Seating arrangement]
|
SR.No
|
ENROLLMENT NO.
|
SUB
|
Total
|
Classroom
|
|
1
|
140220107002 to 140220107106
|
IP
|
18
|
314
|
|
2
|
140220107021 to 150223131042
|
DDBMS
|
27
|
316
|
|
3
|
110220131109 to 140220107076
|
DMBI
|
36
|
306
|
|
4
|
140220107077 to 150223131035
|
DMBI
|
37
|
307
|
Note: It is here by informed to all
students that they should remain present in mentioned classroom 10 min before
Examination Time.
Exam-
coordinator H.O.D
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